1. Field of the Invention
This invention relates to an Ethernet signal receiving device and the control method thereof, especially to a signal receiving device with noise cancellers and methods of controlling the signal receiving device.
2. Description of Related Art
FIG. 1 shows a partial functional block diagram of a prior-art receiving device used in network systems. The receiving device 100 includes a front-end receiving circuit 110, a noise cancelling circuit 120, a feed-forward equalizer (FFE) 130, a digital automatic gain control (DAGC) circuit 140, a feed-back equalizer (FBE) 150 and a post-processing circuit 160.
The front-end receiving circuit 110 is to receive an analog input signal from a remote end and transforms it into a digital signal. The front-end receiving circuit 110 includes an analog automatic gain control (AAGC) circuit and an analog-to-digital converter (ADC). The AAGC circuit automatically adjusts amplitudes of the input signal in order that the adjusted input signal has better amplitudes to facilitate the processing of post circuits. The ADC converts the input signal from analog domain to digital domain. In addition to the AAGC circuit and the ADC, the front-end receiving circuit 110 may include other circuits, such as a filtering circuit and a sampling/holding circuit.
The noise cancelling circuit 120 is to cancel the noises in the input signal of a channel belonging to a port. The noises are probably an echo signal of the channel, a near-end cross talk (NEXT) interference from another channel of the same port, or an alien NEXT interference from a port adjacent to the port to which the channel belongs. Echo signals occur in network applications where a channel has receiving and transmitting capabilities, such as a Multi-port Gigabit Ethernet and a Multi-port Automatic BroadR-Reach Physical Layer (BRPHY) Ethernet; NEXT interferences occur in network applications where a single port has multiple channels, such as the Multi-port Gigabit Ethernet and a Multi-port Fast Ethernet; and the alien NEXT interferences occur in network applications where multiple ports exist, such as the Multi-port Gigabit Ethernet, the Multi-port Automatic BRPHY Ethernet and the Multi-port Fast Ethernet. The noise cancelling circuit 120 includes different noise cancellers that cancel corresponding interferences. For example, an echo canceller is to cancel echo signals, a NEXT canceller is to cancel NEXT interferences, and an alien NEXT canceller is to cancel alien NEXT interferences. In general, the echo canceller, the NEXT canceller and the alien NEXT canceller have filters, and the coefficients of each filter have to be properly adjusted to achieve better noise cancelling effects.
The feed-forward equalizer (FFE) 130 is to eliminate a precursor part of the inter-symbol interferences (ISI) of the input signal while the feed-back equalizer (FBE) 150 is to eliminate a postcursor part of the ISI. For example, the feed-back equalizer (FBE) 150 may include a finite impulse response filter and an infinite impulse response filter. Likewise, the finite impulse response filter and the infinite impulse response filter have filter coefficients, which should be timely updated and trained to make the filter operate in an expected way. If, however, two or more noise cancellers or equalizers keep updating or training their individual filter coefficients by the same data code for a certain period of time, the filter coefficients of the noise canceller or the equalizers interfere with each other, which cause the filter coefficients to be not able to converge properly. This phenomenon is referred to as seed collision. Proper processes that handle seed collision are required to assure that the noise cancellers and the equalizers can work normally.
The DAGC circuit 140 is to adjust the energy of the signal in digital domain in order that the energies of the adjusted signals become uniform to facilitate the process of the post-processing circuit 160. The post-processing circuit 160 includes other circuits of the receiving device 100, such as a slicer and a decision-feedback sequence estimation (DFSE) circuit (not shown). The output of the slicer is transmitted to the feed-back equalizer (FBE) 150 and the DFSE circuit generates data carried by the input signal.
The AAGC circuit and the digital automatic gain control circuit can be implemented by programmable gain amplifiers (PGA). In general, the setting parameters of the PGAs do not change after an initialization process. Unfortunately, a dramatic change in the ambient temperature of the receiving device 100, such as in a car environment, causes big changes in the insertion loss, which forces the setting parameters of the PGAs to be adjusted correspondingly to avoid clipping of the ADC. However, when the setting parameters of the PGAs change, filter coefficients of the noise canceller or the equalizer must be adjusted accordingly. The adjusting process may probably conflict the seed collision handling processes, causing failure in timely updating the filter coefficients; therefore the receiving device 100 cannot operate effectively or accurately.